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M74HCT646 M74HCT648
HCT646 OCTAL BUS TRANSCEIVER/REGISTER (3-STATE) HCT648 OCTAL BUS TRANSCEIVER/REGISTER (3-STATE, INV.)
.HI .LOWPOWERDI .COMPATI .OUTPUTDRI .SYMMETRI .BALANCEDPROPAGATI .PI
GH SPEED fMAX = 60 MHz (TYP.) AT VCC = 5 V SSIPATION ICC = 4 A (MAX.) AT TA = 25 C BLE WITH TTL OUTPUTS VIH = 2V (MIN.) VIL = 0.8V (MAX) VE CAPABILITY 15 LSTTL LOADS CAL OUTPUT IMPEDANCE IOH= IOL = 6 mA (MIN.) ON DELAYS tPLH = tPHL N AND FUNCTION COMPATIBLE WITH 54/74LS646/648
B1R (Plastic Package)
M1R (Micro Package)
ORDER CODES : M74HCTXXXM1R M74HCTXXXB1R
DESCRIPTION The M74HCT646/648 are high speed CMOS OCTAL BUS TRANSCEIVERS AND REGISTERS, 2 (3-STATE) fabricated in silicon gate C MOS technology. They have the same high speed performance of LSTTL combined with true CMOS low power consumption. These devices consist of bus transceiver circuits with 3-state output, D-type flip-flops, and control circuitry arranged for multiplexed transmission of data directly from the input bus or from the internal registers. Data on the A or B bus will be clocked into the registers on the lowto-high transition of the appropriate clock pin (Clock AB - or Clock BA). Enable (G) and direction (DIR) pins are provided to control the transceiver functions. In the transceiver mode, data present at the high-impedance port may be stored in either register or in both. The select controls (Select AB select BA) can multiplex stored and real-time (transparent mode) data. The direction control determines which bus will receive data when enable G is active (low). In the isolation mode (enable G high), "A" data may be stored in one register and/or "B" data may be stored in the other register. When an output function is disabled, the input function is still enabled and may be used to store and transmit data. Only one of the two buses, A or B, may be driven at a time. All inputs are equipped with protection circuits against static discharge and transient excess voltage.This integrated circuit has input and output characteristics that are fully compatible with 54/74 LSTTL logic families. M74HCT devices are designed to directly interface HSC2MOS systems with TTL and NMOS components. They are also plug in replacements for LSTTL devices giving a reduction of power consumption.
October 1993
PIN CONNECTIONS (top view)
INPUT AND OUTPUT EQUIVALENT CIRCUIT
GAB, GAB, CAB, SAB, SBA, CBA A, B
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M74HCT646/648
LOGIC DIAGRAM (HCT648)
Note : In case of M54/74HCT646 output inverter marked * at A bus and B bus are eliminated.
TIMING CHART
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M74HCT646/648
TRUTH TABLE HCT646 (The truth table for HCT648 is the same as this, but with the outputs inverted)
G DIR CAB CBA SAB SBA X H X X X X X X A INPUTS Z INPUTS B INPUTS Z INPUTS FUNCTION Both the A bus and the B bus are inputs The output functions of the A and B bus are disabled Both the A and B bus are used for inputs to the internal flip-flops. Data at the bus will be stored on low to high transition of the clock inputs The A bus are inputs and the B bus are outputs The data at the A bus are displayed at the B bus The data at the A bus are displayed at the B bus. The data of the A bus are stored to the internal flip-flop on low to high transition of th clock pulse. The data stored to the internal flip-flop are dispayed at the B bus The data at the A bus are stored to the internal flipflop on low to high transition of the clock pulse. The states of the internal flip-flops output directly to the B bus The A bus are outputs and the B bus are inputs The data at the B bus are displayed at the A bus The data at the B bus are displayed at the A bus. The data of the B bus are stored to the internal flipflop on low to high transition of the clock pulse The data stored to the internal flip-flops are displayed at the B bus the data at the B bus are stored to the internal flipflop on low to high transition of the clock pulse. The states of the internal flip-flops output directly to the A bus
X
X* X*
L L
X X
iNPUTS L H L H X L H
OUTPUTS L H L H Qn L H
L
H X X* X* H H X X
OUTPUTS X* X* L L X* x* X X X H H X X X L L L H L H Qn L H
INPUTS L H L H X L H
X : DON'T CARE Z : HIGH IMPEDANCE Qn : THE DATA STORED TO THE INTERNAL FLIP-FLOPS BY MOST RECENT LOW TO HIGH TRANSITION OF THE CLOCK INPUTS * : THE DATA AT THE A AND B BUS WILL BE STORED TO THE INTERNAL FLIP-FLOPS ON EVERY LOW TO HIGH TRANSITION OF THE CLOCK INPUTS
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M74HCT646/648
PIN DESCRIPTION
PIN No 1 2 3 4, 5, 6, 7, 8, 9, 10, 11 20, 19, 18, 17, 16, 15, 14, 13 21 22 23 12 24 SYMBOL CLOCK AB SELECT AB DIR A1 to A8 B1 to B8 G SELECT BA CLOCK BA GND VCC NAME AND FUNCTION A to B Clock Input (LOW to HIGH, Edge-Trigged) Select A to B Source Input Direction Control Input A data Inputs/Outputs B Data Inputs/Outputs Output Enable Input (Active LOW) Select B to A Source Input B to A Clock Input (LOW to HIGH, Edge-Triggered) Ground (0V) Positive Supply Voltage
IEC LOGIC SYMBOLS
HCT646 HCT648
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M74HCT646/648
ABSOLUTE MAXIMUM RATINGS
Symbol VCC VI VO IIK IOK IO ICC or IGND PD Tstg TL Supply Voltage DC Input Voltage DC Output Voltage DC Input Diode Current DC Output Diode Current DC Output Source Sink Current Per Output Pin DC VCC or Ground Current Power Dissipation Storage Temperature Lead Temperature (10 sec) Parameter Value -0.5 to +7 -0.5 to VCC + 0.5 -0.5 to VCC + 0.5 20 20 35 70 500 (*) -65 to +150 300 Unit V V V mA mA mA mA mW
o o
C C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these condition isnotimplied. (*) 500 mW: 65 oC derate to 300 mW by 10mW/oC: 65 oC to 85 oC
RECOMMENDED OPERATING CONDITIONS
Symbol VCC VI VO Top tr, tf Parameter Supply Voltage Input Voltage Output Voltage Operating Temperature Input Rise and Fall Time (VCC = 4.5 to 5.5V) Value 4.5 to 5.5 0 to VCC 0 to VCC -40 to +85 0 to 500 Unit V V
o
V C
ns
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M74HCT646/648
DC SPECIFICATIONS
Test Conditions Symbol VIH Parameter High Level Input Voltage VCC (V) 4.5 to 5.5 4.5 to 5.5 4.5 VI = IO=-20 A VIH IO=-6.0 mA or V IL VI = IO= 20 A VIH IO= 6.0 mA or V IL VI = VCC or GND VI = VCC or GND 4.4 4.18 4.5 4.31 Value TA = 25 oC Min. Typ. Max. 2.0 -40 to 85 oC Min. Max. 2.0 Unit V
V IL
Low Level Input Voltage High Level Output Voltage
0.8
0.8
V
V OH
4.4 4.13 V
VOL
Low Level Output Voltage 4.5
0.0 0.17
0.1 0.26
0.1 0.33
V A A A mA
II ICC IOZ ICC
Input Leakage Current (*) Quiescent Supply Current Output Off-state Current Additional worst case supply current
5.5 5.5
0.1 4 ae0.5 2.0
1 40 5 2.9
5.5 VO = VCC or GND VI = VIH or V IL 5.5 Per Input pin VI = 0.5V or V I = 2.4V Other Inputs at V CC or GND IO= 0
(*): Applicable only to DIR, G, CAB, CBA, SBA input.
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M74HCT646/648
AC ELECTRICAL CHARACTERISTICS (C L = 50 pF, Input t r = tf = 6 ns)
Test Conditions Symbol Parameter VCC (V) 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 4.5 CL (pF) 50 50 150 50 150 50 150 50 150 50 50 50 50 50 RL = 1 K RL = 1 K RL = 1 K 31 Value TA = 25 C -40 to 85 oC 54HC and 74HC 74HC
o
Unit
Min.
Typ. 7 20 25 29 34 24 29 26 31 26 55 8 3 5 13
Max. 12 30 38 44 52 34 42 38 46 35
Min.
Max. 15 38 48 55 65 43 53 48 58 44 ns ns ns ns ns ns ns ns ns ns MHz 19 13 5 10 ns ns ns pF pF pF
tTLH tTHL tPLH tPHL tPLH tPHL tPLH tPHL tPZL tPZH tPLZ tPHZ fMAX tW(H) tW(L) ts th CIN CI/O CPD (*)
Output Transition Time Propagation Delay Time (BUS - BUS) Propagation Delay Time (CLOCK - BUS) Propagation Delay Time (SELECT - BUS) 3-State Output Enable Time (G, DIR - BUS) 3-State Output Disable Time (G, DIR - BUS) Maximum Clock Frequency Minimum Pulse Width Minimum Set-up Time Minimum Hold Time Input Capacitance Bus Terminal Capacitance Power Dissipation Capacitance
25 15 10 5 10
for HCT646 for HCT648
40 39
(*) CPD is defined as the value of the IC's internal equivalent capacitance which is calculated from the operating current consumption without load. (Refer to Test Circuit). Average operting current can be obtained by the following equation. ICC(opr) = CPD *VCC *fIN + ICC/8 (per bit)
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M74HCT646/648
SWITCHING CHARACTERISTICS TEST CIRCUIT AND WAVEFORM WAVEFORM 1 WAVEFORM 2
WAVEFORM 3
WAVEFORM 4
WAVEFORM 5
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M74HCT646/648
TEST WAVEFORM ICC (Opr.)
* INPUT TRANSITION TIME IS THE SAME AS THAT IN CASE OF SWITCHING CHARACTERISTICSTEST.
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M74HCT646/648
Plastic DIP24 (0.25) MECHANICAL DATA
mm MIN. a1 b b1 b2 D E e e3 F I L 4.445 3.3 15.2 2.54 27.94 14.1 0.175 0.130 0.23 1.27 32.2 16.68 0.598 0.100 1.100 0.555 TYP. 0.63 0.45 0.31 0.009 0.050 1.268 0.657 MAX. MIN. inch TYP. 0.025 0.018 0.012 MAX.
DIM.
P043A
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M74HCT646/648
SO24 MECHANICAL DATA
mm MIN. A a1 a2 b b1 C c1 D E e e3 F L S 7.40 0.50 15.20 10.00 1.27 13.97 7.60 1.27 8 (max.) 0.291 0.19 15.60 10.65 0.35 0.23 0.50 45 (typ.) 0.598 0.393 0.05 0.55 0.299 0.050 0.614 0.420 0.10 TYP. MAX. 2.65 0.20 2.45 0.49 0.32 0.013 0.009 0.020 0.004 MIN. inch TYP. MAX. 0.104 0.007 0.096 0.019 0.012
DIM.
L C c1
a2
A
e3
E
D
24
13
1
12
F
a1
b
e
s
b1
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M74HCT646/648
Information furnished is believed to be accurate and reliable. However, SGS-THOMSON Microelectronics assumes no responsability for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may results from its use. No license is granted by implication or otherwise under any patent or patent rights of SGS-THOMSON Microelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. SGS-THOMSON Microelectronics products are not authorized for use ascritical components in life support devices or systems without express written approval of SGS-THOMSON Microelectonics. (c) 1994 SGS-THOMSON Microelectronics - All Rights Reserved SGS-THOMSON Microelectronics GROUP OF COMPANIES Australia - Brazil - France - Germany - Hong Kong - Italy - Japan - Korea - Malaysia - Malta - Morocco - The Netherlands Singapore - Spain - Sweden - Switzerland - Taiwan - Thailand - United Kingdom - U.S.A
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